1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to semiconductor memory devices having reduced standby failures.
2. Description of the Related Art
Standby failure occurs when current leakage through a current path in an integrated circuit persists following a defined operating mode. Under these circumstances, the current leakage wastes power, which is particularly detrimental to mobile electronics incorporating the semiconductor device, and may be erroneously interrupted as a signal within the semiconductor device.
For example, semiconductor memory devices include a cell core and one or more related peripheral circuits. Common operating modes for contemporary semiconductor memory devices include an active mode and a standby mode. In active mode, data may be written to or read from memory cells in the cell core by controlled operation of the related peripheral circuits. However, in standby mode, the peripheral circuits are specifically disabled in order to reduce power consumption within the semiconductor memory device. Thus, a standby failure occurring in such peripheral circuits defeats, as least in part, the primary purpose of the standby operating mode.
FIG. 1 is a circuit diagram illustrating a relevant portion of a peripheral circuit 100 in a conventional semiconductor memory device. As shown in FIG. 1, peripheral circuit 100 receives a clock signal CLK and a plurality of data signals D0, D1, . . . Dn. During a write operation, the peripheral circuit will drive the plurality of signals onto signal lines connected to memory cells on the cell core of the semiconductor memory device (not shown). In order to drive the plurality of data signals to the cell core, a relatively large number of peripheral circuit components must be used. These components perform various, well-understood functions and may be variously implemented and operated within the semiconductor memory device. Generally speaking, however, many of the peripheral circuit components will include a combination or sequential logic circuit operating in relation to one or more input signals and providing a corresponding output. Many of the peripheral circuit components also include one or more flip-flop circuits.
Referring to the collection of peripheral circuit components 100 shown in FIG. 1, when power is applied to the constituent semiconductor memory device, an initialization process is performed. During the initialization process, defined “set” (SN) and “reset” (RN) are generated upon detection of the applied power. As the set/reset signals are applied to the peripheral circuit components during the initialization process, default state outputs are provided by the peripheral circuit components. A test process may be applied to the semiconductor memory device during a first (or each) initialization process. During the test process, a predetermined data pattern is applied to the collection of peripheral circuit components 100. With the predetermined data pattern applied, the current consumption of the semiconductor memory device is measured and a determination is made regarding whether or not excessive current leakage is present (i.e., whether a standby failure has occurred). However, this static default condition testing is often unable to accurately identify current leakage associated with mode transitions within the semiconductor memory device.
FIG. 2 illustrates one example of current leakage occurring in the peripheral circuit components 100 of FIG. 1 in relation to an operating mode transition. Following a read/write operation performed by the semiconductor memory device, the data output state for the individual peripheral circuit components 110, 120 and 130 will have random values as the semiconductor memory device enters a subsequent standby mode. For example, if an electrical connection exists between the output of a first peripheral circuit component 110 and a first external signal line, a current path may exist, depending on the residual data state apparent at the output (i.e., its residual voltage state as defined by the last read/write operation) and the voltage level apparent on the first external signal line. Current paths formed in the direction of the illustrated arrows shown in FIG. 2 may exist given the respective residual data states of the first, second and third peripheral circuit components 110, 120 and 130. Thus, since a “low” data state (and a corresponding low voltage) is apparent at the output of the NAND gate of the first and third peripheral circuit components 110 and 130, a current path may be formed when the first or third external signal lines is respectively connected to a “high” voltage source. In similar vein, since a “high” data state (and a corresponding high voltage) is apparent at the output of the NOR gate of the second peripheral circuit component 120, a current path may be formed when the second external signal line is connected to a “low” voltage source (i.e., ground).
Thus, even where current leakage in peripheral circuit components is not detected during initialization testing under static default conditions, a standby failure may nonetheless occur when certain residual data values are apparent at the outputs of the peripheral circuit components, when said outputs are connected to external signal lines coincidentally connected to a mismatched power voltage, for example. Under these dynamic, data-sensitive conditions arising from a previously performed active mode operation, a standby failure may arise that consumes excessive power and reduces overall battery life in portable electronics incorporating the semiconductor device.